The delay-locked loop (DLL) technology, which is achieved by improving the PLL technology, is widely applied in the timing field. The DLL has inherited the phase lock technology for PLL circuit, but removed the oscillator section within the PLL circuit, which is replaced by a delay line whose delay amount can be controlled. Compared with the PLL, the DLL has no jitter accumulation, but has a shorter locking time and the advantage that the loop filter can be easily integrated and so on.
A clock Duty Cycle Corrector (DCC) circuit is used for adjusting the duty cycle of a signal. The DCC can be used together with the DLL, thereby the duty cycle of an output signal can be adjusted to 50%.
FIG. 1 is a schematic diagram of the circuit structure of a high-frequency delay-locked loop in the prior art, wherein the high-frequency delay-locked loop is implemented by a DLL/DCC circuit structure. The operation principle of the DLL is that an input clock is delayed via a DLL delay chain to form a first clock (clock_000), the first clock (clock_000) is delayed via a first DCC delay chain (DCC delay chain 1) to form a second clock (clock_180), and the second clock (clock_180) is delayed via a second DCC delay chain (DCC delay chain 2) to form a third clock (clock_360). The DCC delay chain 1 and the DCC delay chain 2 are the same. The second clock (clock_180) has a phase delay of 180° relative to the first clock (clock_000), and the third clock (clock_360) has a phase delay of 180° relative to the second clock (clock_180). A feedback clock is formed after the first clock (clock_000) and the second clock (clock_180) pass through a clock combining circuit in the DCC circuit and a feedback circuit, and the phase of the input clock is compared with the phase of the feedback clock in a DLL phase detector. The DLL phase detector controls a DLL logic control circuit based on the comparison result, so that the DLL logic control circuit controls the DLL delay chain to increase or decrease the delay length thereof until the phase of the input clock is aligned with the phase of the feedback clock.
As to the DCC circuit, as described above, the first clock (clock_000) is input into the DCC, and the second clock (clock_180) and the third clock (clock_360) are generated after the first clock passes through two identical delay chains, i.e. the DCC delay chain 1 and the DCC delay chain 2. The phase of the first clock (clock_000) is compared with the phase of the third clock (clock_360) in the DCC phase detector, which controls the DCC logic control circuit based on the phase comparison result, so that the DCC logic control circuit controls the DCC delay chain 1 and the DCC delay chain 2 to increase or decrease the delay length thereof respectively until the phase of the first clock (clock_000) is aligned with the phase of the third clock (clock_360).
FIG. 2 is a timing control diagram of the operation principle of the DCC in the high-frequency delay-locked loop of FIG. 1. As shown in FIG. 2, when the DCC is locked, the rising edge of the first clock (clock_000) is aligned with the rising edge of the third clock (clock_360). Since the DCC delay chain 1 and the DCC delay chain 2 are completely the same, the delay between the rising edge of the second clock (clock_180) and the rising edge of the first clock (clock_000) is exactly half of the clock period. The first clock (clock_000) and the second clock (clock_180) are input into the clock combining circuit, wherein the rising edge of the first clock (clock_000) generates the rising edge of the output clock and the rising edge of the second clock (clock_180) generates the falling edge of the output clock. Thus the duty cycle of the output clock is 50%, i.e. the correction to the duty cycle of the clock is achieved.
In the prior art, the following problems exist in the DLL/DCC circuit structure as described above: although the DLL/DCC circuit of such structure can guarantee the phase and the duty cycle (50%) of the output clock, for example, when the input clock has a very high frequency and a very small duty cycle (for example, the input clock has a clock period TCK=1 ns, a duty cycle of 30%, and a high level width of 300 ps), the input clock will be lost after passing through the DLL delay chain, the DCC delay chain 1 and the DCC delay chain 2 due to duty cycle distortion of the clock delay chains, resulting in an error in the output clock. That is, after the clock with a high level of 300 ps is delayed, the high level will disappear and a predetermined output clock cannot be obtained. Similarly, if the low level width of the input clock is too small, the low level will disappear after the input clock passes through the DLL delay chain, the DCC delay chain 1 and the DCC delay chain 2 and a predetermined output clock cannot be obtained either.